High precision analog floating gate voltage reference circuits are described in U.S. Pat. No. 6,847,555, issued Jan. 25, 2005, which is incorporated by reference herein. The operating principles of high precision CMOS floating gate analog voltage references are also described in an article by Ahuja, B. K., et al., entitled “A very high precision 500-nA CMOS floating-gate analog voltage reference”, IEEE Journal of Solid-State Circuits, Volume 40, Issue 12, December 2005 Page(s): 2364-2372, which is incorporated by reference herein. FIG. 1A is an illustrative prior art equivalent circuit diagram 10 for the floating gate reference circuit. As described in the Ahuja reference identified above, two tunneling elements, tunnel diodes T1 and T2, are needed to set a fixed voltage on the floating gate node at the junction therebetween. Basically, using Fowler-Nordheim tunneling through the inter-poly oxide, the tunneling element T1 is used to charge the floating gate node during programming by raising VP, and by lowering VN, the tunneling element T2 is used to discharge the floating gate node. When the voltage on the floating gate node reaches the desired set level, both of the tunneling elements are turned off by making VP and VN about zero volts. Thus, a fixed charge is stored permanently on the floating gate for normal operation of the device.
FIG. 1B is a cross-sectional view and exemplary circuit diagram illustrating the series connected tunneling elements T1 and T2 in FIG. 1A. The prior art equivalent circuit diagram is shown at 20 and the physical implementation cross-section is shown at 30. As seen in the cross section, there is a polysilicon layer (poly1) and another polysilicon layer (poly2) layer formed on a substrate along with two electron tunneling regions. In two predetermined locations which define these tunneling regions, the poly2 layer overlaps the poly1 layer with a thin oxide dielectric between them. Typically, polysilicon layers 1 and 2 are separated from each other by about 400 A of oxide dielectric, with the floating gate, FG, being completely surrounded by dielectric. The electrically isolated floating gate comprises the poly1 layer and poly2 layer connected together, as shown at contact region 70. At the poly1/poly2 edges, enhanced emission tunneling occurs at tunneling voltages of about 10-12 V. Both tunnel regions have a given capacitance.
One drawback of the physical implementation shown in FIG. 1B is that its formation requires a special non-standard CMOS process that does not lend itself to simple analogue design. That is, the special process requiring for forming the structure in FIG. 1B does not utilize well known and less costly general purpose CMOS technology, also referred to herein as standard CMOS processes. Another drawback of this implementation is the inability of the process to completely cover the floating gate element with a conductive layer and thus isolate the floating gate from the overlying dielectrics. As a result of this, low concentrations of mobile and polarization charges that are always present in the dielectric over the floating gate may affect the amount of charge stored in the floating gate. It is thus desired to construct the tunnel diode structure using general purpose CMOS technology which provides for a full enclosure of the floating gate element. A memory device that includes floating-gate based capacitor and transistor elements formed using standard CMOS processes is described in co-pending application, “A multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide”, application Ser. No. 11/498,672, which is incorporated by reference herein. There is a need for using general purpose CMOS technology for constructing a tunneling element structure that is usable for a high precision voltage reference circuit.
Floating gate based devices required to store a precise amount of charge on the floating gate (as in floating gate reference circuits) are highly susceptible to the presence of low density mobile ions and polarization charges that are always present in dielectrics deposited over the floating gate. Mobile and polarization charge densities are usually not sufficient to adversely affect circuit performance for devices that do not need high precision voltages. For instance, such effects do not adversely affect circuit performance of the memory device described in the aforementioned co-pending application. In contrast, to provide a high precision floating gate voltage reference circuit, the floating gate is required to be shielded from the overlaying dielectrics in order to minimize the reaction of stored charge with mobile and polarization charges. A drawback of known methods using standard CMOS processes is that they do not provide the required shielding of the floating gate necessary for high precision floating gate voltage reference circuits.
A floating gate shield is commonly formed by the coupling capacitor polysilicon layer present in most EEPROM or flash EEPROM technologies. A drawback of this known method is that EEPROM technologies do not provide the device set required for precision analog voltage reference circuits and for achieving high levels of integration. The high levels of integration required for high precision circuits can be accomplished by embedding the EEPROM in a general purpose CMOS technology. A drawback of this embedding process is that is it very costly, due primarily to the large number of additional process operations required. Another drawback is that, when utilizing the known available structures, small regions of the floating gate node may be unshielded resulting in degraded performance.
There is therefore a need for a device and corresponding method of constructing a structure using general purpose CMOS technology that provides both Fowler-Nordheim tunneling functionality and a shielded floating gate needed for a high precision floating gate voltage reference.